drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35

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[Why]
3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers
now exist in MCM state.

[How]
Add guards when reading DPP state based on whether the register has a
valid offset.

Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nicholas Kazlauskas 2024-05-21 10:41:52 -04:00 • committed by Alex Deucher

parent 06cd6d8f80

commit 470679ef33

1 changed files with 15 additions and 14 deletions

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drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

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