coresight: trbe: Add ISB after TRBLIMITR write

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[ Upstream commit 52c0164b25 ]

DEN0154 states that hardware will be allowed to ignore writes to TRB*
registers while the trace buffer is enabled. Add an ISB to ensure that
it's disabled before clearing the other registers.

This is purely defensive because it's expected that arm_trbe_disable()
would be called before teardown which has the required ISB.

Fixes: a2b579c41f ("coresight: trbe: Remove redundant disable call")
Signed-off-by: James Clark <james.clark@linaro.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250609-james-cs-trblimitr-isb-v1-1-3a2aa4ee6770@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>

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James Clark 2025-06-09 11:19:05 +01:00 • committed by Greg Kroah-Hartman

parent cc345a2114

commit 471f4ece20

1 changed files with 1 additions and 0 deletions

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drivers/hwtracing/coresight/coresight-trbe.c

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