KVM: PPC: Book3S HV P9: Fixes for TM softpatch interrupt NIP

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The softpatch interrupt sets HSRR0 to the faulting instruction +4, so
it should subtract 4 for the faulting instruction address in the case
it is a TM softpatch interrupt (the instruction was not executed) and
it was not emulated.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210811160134.904987-4-npiggin@gmail.com

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Nicholas Piggin 2021-08-12 02:00:37 +10:00 • committed by Michael Ellerman

parent daac40e8d7

commit 4782e0cd0d

1 changed files with 15 additions and 2 deletions

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arch/powerpc/kvm/book3s_hv_tm.c

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