clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock

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According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

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Samuel Holland 2019-12-28 20:59:20 -06:00 • committed by Maxime Ripard

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commit 47d64fef1f

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drivers/clk/sunxi-ng/ccu-sun8i-r.c

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