drm/amd/display: Set max TTU on DPG enable

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[WHY]
There is a bug in HW that causes P-State to hang when DPG is enabled in
certain conditions.

[HOW]
The solution is to force MIN_TTU_VBLANK register to maximum value
whenever DPG has been enabled.
Make stream do a full update on test pattern change, so that the TTUs
get updated.
When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each
pipe in the stream's topology to the maximum value (0xffffff).

v2: squash in build fix for when DCN is not defined (Alex)

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Wesley Chalmers 2021-03-12 21:47:13 -05:00 • committed by Alex Deucher

parent b126a69906

commit 482812d566

2 changed files with 25 additions and 7 deletions

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31

drivers/gpu/drm/amd/display/dc/core/dc.c

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1

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

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