media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search

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The external clock frequency times the PLL multiplier may exceed the value
range of 32-bit unsigned integers. Instead perform the same calculation y
using two divisions.

The result has some potential to be different, but that's ok: this number
is used to limit the range of pre-PLL divisors to find optimal values. So
the effect of the rare case of a different result here would mean an
invalid pre-PLL divisor is tried. That will be found out a little later in
any case.

Also guard against dividing by zero if the external clock frequency is
higher than the maximum OP PLL output clock --- a rather improbable case.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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Sakari Ailus 2020-07-07 10:31:56 +02:00 • committed by Mauro Carvalho Chehab

parent fe52ece8d2

commit 482e75e7b3

1 changed files with 9 additions and 2 deletions

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drivers/media/i2c/ccs-pll.c

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