drm/i915/display: Handle VSYNC timing in LRR path

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LRR already updates crtc_vtotal/crtc_vblank_end seamlessly.
Extend the same handling to crtc_vsync_start/crtc_vsync_end so
VSYNC timing changes are programmed and accepted via the LRR path instead
of forcing a full modeset.

v2: Add comment explaining why TRANS_VSYNC update is safe for DP LRR.
    (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260609025325.1128543-2-ankit.k.nautiyal@intel.com

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Ankit Nautiyal 2026-06-09 08:23:24 +05:30

parent b7d51d65e4

commit 485356a428

1 changed files with 14 additions and 2 deletions

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drivers/gpu/drm/i915/display/intel_display.c

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