drm/bridge: it6505: update usleep_range for RC circuit charge time

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[ Upstream commit 8814444e62 ]

The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
circuit need at least 25ms for rising time, update for match spec

Signed-off-by: Kuro Chung <kuro.chung@ite.com.tw>
Signed-off-by: Hermes Wu <hermes.wu@ite.com.tw>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240604024405.1122488-1-kuro.chung@ite.com.tw
Stable-dep-of: c5f3f21728 ("drm/bridge: it6505: Fix inverted reset polarity")
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Kuro Chung 2024-06-04 10:44:05 +08:00 • committed by Greg Kroah-Hartman

parent f454a3e98c

commit 4859245543

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/bridge/ite-it6505.c

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