pwm: jz4740: Improve algorithm of clock calculation

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The previous algorithm hardcoded details about how the TCU clocks work.
The new algorithm will use clk_round_rate to find the perfect clock rate
for the PWM channel.

This code relies on the fact that clk_round_rate() will always round
down, which is not a valid assumption given by the clk API, but only
happens to be true with the clk drivers used for Ingenic SoCs.

Right now, there is no alternative as the clk API does not have a
round-down function (and won't have one for a while), but if it ever
comes to light, a round-down function should be used instead.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

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Paul Cercueil 2020-03-23 15:24:19 +01:00 • committed by Thierry Reding

parent ce1f9cece0

commit 485b56f08f

1 changed files with 29 additions and 15 deletions

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drivers/pwm/pwm-jz4740.c

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