drm/amd/display: Reset DMUB mailbox SW state after HW reset

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[ Upstream commit 154711aa57 ]

[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.

[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Nicholas Kazlauskas 2023-01-20 11:14:30 -05:00 • committed by Greg Kroah-Hartman

parent 383e32fa27

commit 488770cbdd

1 changed files with 12 additions and 0 deletions

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drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

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