mlxsw: reg: Replace MID related fields in SFGC register

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SFGC register maps {packet type, bridge type} -> {MID base, table type}.
As preparation for unified bridge model, remove 'mid' field and add
'mid_base' field.

The MID index (index to PGT table which maps MID to local port list and
SMPE index) is a result of 'mid_base' + 'fid_offset'. Using the legacy
bridge model, firmware configures 'mid_base'. However, using the new model,
software is responsible to configure it via SFGC register.

The 'mid_base' is configured per {packet type, bridge type}, for
example, for {Unicast, .1Q}, {Broadcast, .1D}.

Add the field 'mid_base' to SFGC register and increase the length of the
register accordingly.

Remove the field 'mid' as currently it is ignored by the device, its use
is an old leftover.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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This commit is contained in:

Amit Cohen 2022-06-19 13:29:17 +03:00 • committed by David S. Miller

parent 94536249b8

commit 48bca94fff

2 changed files with 9 additions and 10 deletions

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2

drivers/net/ethernet/mellanox/mlxsw/port.h

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17

drivers/net/ethernet/mellanox/mlxsw/reg.h

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