ASoC: wm8940: Fix setting PLL Output clock division ratio

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According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

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Axel Lin 2011-10-24 11:32:41 +08:00 • committed by Mark Brown

parent 753ddf5215

commit 49fa4d9b5a

1 changed files with 2 additions and 2 deletions

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sound/soc/codecs/wm8940.c

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