clk: eyeq: add fixed factor clocks infrastructure

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Driver can currently host two types of clocks:
 - PLLs derived directly from the main crystal (taken using a fwhandle).
 - Divider clocks derived from those PLLs.

PLLs can be instantiated from of_clk_init() or platform device probe,
using two separate clock providers. Divider clocks are all instantiated
at platform device probe.

Add a third type of clocks: fixed factors. Those can be instantiated at
both stages. They can be parented to any clock from the driver. Early
match data and match data store the list of fixed factor clocks.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-5-84cfefb3f485@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Théo Lebrun 2024-11-06 17:03:56 +01:00 • committed by Stephen Boyd

parent d75fbc82ee

commit 4a1ae0486d

1 changed files with 73 additions and 8 deletions

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drivers/clk/clk-eyeq.c

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