drm/i915/guc: New GuC interrupt register for Gen11

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Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.

Bspec: 21043

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-9-michal.wajdeczko@intel.com

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Michal Wajdeczko 2019-05-27 18:36:04 +00:00 • committed by Chris Wilson

parent afac509284

commit 4a1f9dc119

2 changed files with 14 additions and 1 deletions

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14

drivers/gpu/drm/i915/intel_guc.c

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1

drivers/gpu/drm/i915/intel_guc_reg.h

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