clk: meson: fractional pll support

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Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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This commit is contained in:

Michael Turquette 2016-06-06 18:08:15 -07:00

parent 1c50da4f27

commit 4a47295144

2 changed files with 45 additions and 2 deletions

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32

drivers/clk/meson/clk-pll.c

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15

drivers/clk/meson/clkc.h

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