spi: rockchip: Set rx_fifo interrupt waterline base on transfer item

Browse source

The error here is to calculate the width as 8 bits. In fact, 16 bits
should be considered.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210621104800.19088-4-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Jon Lin 2021-06-21 18:47:57 +08:00 • committed by Mark Brown

parent 0f4f58b847

commit 4a47fcdb5f

No known key found for this signature in database

GPG key ID: 24D68B725D5487D0

1 changed files with 2 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

drivers/spi/spi-rockchip.c

View file