From ba2db535a99dc004ab6b7952625029ec196514b9 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 1 Apr 2015 14:42:00 +0200 Subject: [PATCH 01/17] ARM: dts: lpc18xx: add cgu and ccu clock-controller nodes Add CGU and CCU clock-controller nodes for lpc18xx together with the fixed input clocks. Also remove the temporary fixed-factor pll1 clock from both lpc18xx and lpc4350-hitex-eval DTS now that proper clock drivers are inplace. Signed-off-by: Joachim Eastwood Acked-by: Michael Turquette --- arch/arm/boot/dts/lpc18xx.dtsi | 85 ++++++++++++++++++++---- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 4 -- 2 files changed, 71 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 204da5b52ef9..78292d0cb263 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -13,6 +13,9 @@ #include "armv7-m.dtsi" +#include "dt-bindings/clock/lpc18xx-cgu.h" +#include "dt-bindings/clock/lpc18xx-ccu.h" + / { cpus { #address-cells = <1>; @@ -22,6 +25,7 @@ cpu@0 { compatible = "arm,cortex-m3"; device_type = "cpu"; reg = <0x0>; + clocks = <&ccu1 CLK_CPU_CORE>; }; }; @@ -32,23 +36,76 @@ xtal: xtal { clock-frequency = <12000000>; }; - /* Temporary hardcode PLL1 until clk drivers are merged */ - pll1: pll1 { - compatible = "fixed-factor-clock"; - clocks = <&xtal>; + xtal32: xtal32 { + compatible = "fixed-clock"; #clock-cells = <0>; - clock-div = <1>; - clock-mult = <12>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; }; }; soc { + cgu: clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + ccu1: clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + uart0: serial@40081000 { compatible = "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; status = "disabled"; }; @@ -57,7 +114,7 @@ uart1: serial@40082000 { reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; status = "disabled"; }; @@ -65,7 +122,7 @@ timer0: timer@40084000 { compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; interrupts = <12>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER0>; clock-names = "timerclk"; }; @@ -73,7 +130,7 @@ timer1: timer@40085000 { compatible = "nxp,lpc3220-timer"; reg = <0x40085000 0x1000>; interrupts = <13>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER1>; clock-names = "timerclk"; }; @@ -82,7 +139,7 @@ uart2: serial@400c1000 { reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; status = "disabled"; }; @@ -91,7 +148,7 @@ uart3: serial@400c2000 { reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; status = "disabled"; }; @@ -99,7 +156,7 @@ timer2: timer@400c3000 { compatible = "nxp,lpc3220-timer"; reg = <0x400c3000 0x1000>; interrupts = <14>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER2>; clock-names = "timerclk"; }; @@ -107,7 +164,7 @@ timer3: timer@400c4000 { compatible = "nxp,lpc3220-timer"; reg = <0x400c4000 0x1000>; interrupts = <15>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; }; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index d04072f40817..4ebdb54cc9ce 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -36,10 +36,6 @@ memory { }; }; -&pll1 { - clock-mult = <15>; -}; - &uart0 { status = "okay"; }; From f2b1c507d45f1d4cb4ab296ff0a20b5add6b8bdd Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Fri, 15 May 2015 19:43:45 +0200 Subject: [PATCH 02/17] ARM: dts: lpc18xx: add uart new compat string and clk names Add lpc1850-uart compatible string on uarts together with proper clock-names. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 78292d0cb263..41a3825b09a4 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -101,20 +101,22 @@ ccu2: clock-controller@40052000 { }; uart0: serial@40081000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart1: serial@40082000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + clock-names = "uartclk", "reg"; status = "disabled"; }; @@ -135,20 +137,22 @@ timer1: timer@40085000 { }; uart2: serial@400c1000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; + clock-names = "uartclk", "reg"; status = "disabled"; }; uart3: serial@400c2000 { - compatible = "ns16550a"; + compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; + clock-names = "uartclk", "reg"; status = "disabled"; }; From d881f5e228177355707c95146457d62c5187ea57 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:40:13 +0200 Subject: [PATCH 03/17] ARM: dts: lpc18xx: add pinctrl node Add pinctrl node for lpc1850-scu. Signed-off-by: Joachim Eastwood Acked-by: Linus Walleij --- arch/arm/boot/dts/lpc18xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 41a3825b09a4..32c3feceff6e 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -136,6 +136,12 @@ timer1: timer@40085000 { clock-names = "timerclk"; }; + pinctrl: pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + }; + uart2: serial@400c1000 { compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>; From 7836dce471335fc8e2a09a4015e70f2c9c1554a6 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Mon, 27 Apr 2015 23:59:30 +0200 Subject: [PATCH 04/17] ARM: dts: lpc18xx: add gpio node Add gpio and mapping between pinctrl/gpio namespace with gpio-ranges property. Signed-off-by: Joachim Eastwood Acked-by: Linus Walleij --- arch/arm/boot/dts/lpc18xx.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 32c3feceff6e..60dc929568b3 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -16,6 +16,9 @@ #include "dt-bindings/clock/lpc18xx-cgu.h" #include "dt-bindings/clock/lpc18xx-ccu.h" +#define LPC_PIN(port, pin) (0x##port * 32 + pin) +#define LPC_GPIO(port, pin) (port * 32 + pin) + / { cpus { #address-cells = <1>; @@ -177,5 +180,53 @@ timer3: timer@400c4000 { clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; + + gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, + <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, + <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, + <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, + <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, + <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, + <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, + <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, + <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, + <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, + <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, + <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, + <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, + <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, + <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, + <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, + <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, + <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, + <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, + <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, + <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, + <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, + <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, + <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, + <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, + <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, + <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, + <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, + <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, + <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, + <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, + <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, + <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, + <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, + <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, + <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, + <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, + <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; + }; }; }; From 5d2ea79c7f73c8d57ccbc46e97ff400afd9bfe9b Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 1 Apr 2015 14:41:06 +0200 Subject: [PATCH 05/17] ARM: dts: lpc18xx: add ssp nodes Add nodes for the ARM SSP controllers on lpc18xx. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 60dc929568b3..920cdb26743c 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -123,6 +123,17 @@ uart1: serial@40082000 { status = "disabled"; }; + ssp0: spi@40083000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x40083000 0x1000>; + interrupts = <22>; + clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer0: timer@40084000 { compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; @@ -181,6 +192,17 @@ timer3: timer@400c4000 { clock-names = "timerclk"; }; + ssp1: spi@400c5000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x400c5000 0x1000>; + interrupts = <23>; + clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio: gpio@400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>; From 7e6c8376e9d0db8c825e9fdf95e30b7296c6caa3 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:21:43 +0200 Subject: [PATCH 06/17] ARM: dts: lpc18xx: add can nodes Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 920cdb26743c..813ed93d6570 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -156,6 +156,14 @@ pinctrl: pinctrl@40086000 { clocks = <&ccu1 CLK_CPU_SCU>; }; + can1: can@400a4000 { + compatible = "bosch,c_can"; + reg = <0x400a4000 0x1000>; + interrupts = <43>; + clocks = <&ccu1 CLK_APB1_CAN1>; + status = "disabled"; + }; + uart2: serial@400c1000 { compatible = "nxp,lpc1850-uart", "ns16550a"; reg = <0x400c1000 0x1000>; @@ -203,6 +211,14 @@ ssp1: spi@400c5000 { status = "disabled"; }; + can0: can@400e2000 { + compatible = "bosch,c_can"; + reg = <0x400e2000 0x1000>; + interrupts = <51>; + clocks = <&ccu1 CLK_APB3_CAN0>; + status = "disabled"; + }; + gpio: gpio@400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>; From cd07154f49bb865d619c8db0bdd28c39c70e5870 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:27:33 +0200 Subject: [PATCH 07/17] ARM: dts: lpc18xx: add mmcsd node Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 813ed93d6570..0562f9629b9d 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -68,6 +68,16 @@ gp_clkin: gp_clkin { }; soc { + mmcsd: mmcsd@40004000 { + compatible = "snps,dw-mshc"; + reg = <0x40004000 0x1000>; + interrupts = <6>; + num-slots = <1>; + clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; + clock-names = "ciu", "biu"; + status = "disabled"; + }; + cgu: clock-controller@40050000 { compatible = "nxp,lpc1850-cgu"; reg = <0x40050000 0x1000>; From 16df2b868e516701832ba333734d4d071fafa311 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:31:49 +0200 Subject: [PATCH 08/17] ARM: dts: lpc18xx: add creg (syscon) node The CREG block contains a collection of miscellaneous configuration register like Ethernet phy mode, low power clocks and DMA multiplexer. These registers needs to be accessed from other drivers and syscon provides this capability. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 0562f9629b9d..563435aaee57 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -78,6 +78,12 @@ mmcsd: mmcsd@40004000 { status = "disabled"; }; + creg: syscon@40043000 { + compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; + reg = <0x40043000 0x1000>; + clocks = <&ccu1 CLK_CPU_CREG>; + }; + cgu: clock-controller@40050000 { compatible = "nxp,lpc1850-cgu"; reg = <0x40050000 0x1000>; From fe968589284ecc9a95c6040eea4f3712f0eb1f47 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:29:28 +0200 Subject: [PATCH 09/17] ARM: dts: lpc18xx: add ethernet node Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 563435aaee57..be154749bf56 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -78,6 +78,16 @@ mmcsd: mmcsd@40004000 { status = "disabled"; }; + mac: ethernet@40010000 { + compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; + reg = <0x40010000 0x2000>; + interrupts = <5>; + interrupt-names = "macirq"; + clocks = <&ccu1 CLK_CPU_ETHERNET>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + creg: syscon@40043000 { compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; reg = <0x40043000 0x1000>; From b06cdb7949e421bc511a99e5ca10fe610e21c750 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Sat, 20 Jun 2015 14:45:12 +0200 Subject: [PATCH 10/17] ARM: dts: lpc18xx: add usb nodes Add nodes for the two USB EHCI controllers found on lpc18xx. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index be154749bf56..c17b82cc2d4c 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -78,6 +78,23 @@ mmcsd: mmcsd@40004000 { status = "disabled"; }; + usb0: ehci@40006100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40006100 0x100>; + interrupts = <8>; + clocks = <&ccu1 CLK_CPU_USB0>; + has-transaction-translator; + status = "disabled"; + }; + + usb1: ehci@40007100 { + compatible = "nxp,lpc1850-ehci", "generic-ehci"; + reg = <0x40007100 0x100>; + interrupts = <9>; + clocks = <&ccu1 CLK_CPU_USB1>; + status = "disabled"; + }; + mac: ethernet@40010000 { compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; reg = <0x40010000 0x2000>; From c97a63c9deb50763242d8e6325ac404c823efd05 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:51:20 +0200 Subject: [PATCH 11/17] ARM: dts: lpc4357-ea4357: add pinctrl and uart0 muxing Setup pin muxing and properties for the debug console on uart0. Signed-off-by: Joachim Eastwood Acked-by: Linus Walleij --- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 08a6f757f924..06ba998d544f 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -36,6 +36,26 @@ memory { }; }; +&pinctrl { + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-pull-down; + }; + }; +}; + &uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; From bfd0b498bee4f836610c477cae21aefb16cfe0b1 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:54:29 +0200 Subject: [PATCH 12/17] ARM: dts: lpc4357-ea4357: add mmcsd Enable the MMC/SD controller on EA4357 devkit and add pin muxing plus a regulator. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 47 +++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 06ba998d544f..d02f93f19bf5 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -34,9 +34,48 @@ memory { device_type = "memory"; reg = <0x28000000 0x2000000>; /* 32 MB */ }; + + /* vmmc is controlled by sdmmc host internally */ + vmmc: vmmc_fixed { + compatible = "regulator-fixed"; + regulator-name = "vmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &pinctrl { + sdmmc_pins: sdmmc-pins { + sdmmc_clk_cfg { + pins = "pc_0"; + function = "sdmmc"; + slew-rate = <1>; + bias-pull-down; + }; + + sdmmc_cmd_dat0_3_cfg { + pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10"; + function = "sdmmc"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + sdmmc_cd_cfg { + pins = "pc_8"; + function = "sdmmc"; + bias-pull-down; + input-enable; + }; + + sdmmc_pow_cfg { + pins = "pc_9"; + function = "sdmmc"; + bias-pull-down; + }; + }; + uart0_pins: uart0-pins { uart0_rx_cfg { pins = "pf_11"; @@ -54,6 +93,14 @@ uart0_tx_cfg { }; }; +&mmcsd { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pins>; +}; + &uart0 { status = "okay"; pinctrl-names = "default"; From 95dafb2ca15672ec8e000fcd482fec15e963840e Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:55:32 +0200 Subject: [PATCH 13/17] ARM: dts: lpc4357-ea4357: add gpio joystick Hook up the small joystick found on the EA4357 devkit. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 52 +++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index d02f93f19bf5..ee9d97350d34 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -15,6 +15,9 @@ #include "lpc18xx.dtsi" #include "lpc4357.dtsi" +#include "dt-bindings/input/input.h" +#include "dt-bindings/gpio/gpio.h" + / { model = "Embedded Artists' LPC4357 Developer's Kit"; compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350"; @@ -42,9 +45,58 @@ vmmc: vmmc_fixed { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + gpio_joystick { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_joystick_pins>; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + autorepeat; + + button@0 { + label = "joy_enter"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; + }; + + button@1 { + label = "joy_left"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "joy_up"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; + }; + + button@3 { + label = "joy_right"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; + }; + + button@4 { + label = "joy_down"; + linux,code = ; + gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; + }; + }; }; &pinctrl { + gpio_joystick_pins: gpio-joystick-pins { + gpio_joystick_cfg { + pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + sdmmc_pins: sdmmc-pins { sdmmc_clk_cfg { pins = "pc_0"; From 7de98f2a98c842d1e4805981eff8fdf3c59cdeb0 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Thu, 2 Apr 2015 05:56:57 +0200 Subject: [PATCH 14/17] ARM: dts: lpc4357-ea4357: add ethernet Enable Ethernet and add pin muxing and set the correct frequency on the enet tx clock input. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 73 +++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index ee9d97350d34..0d04a8e8dbc1 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -88,6 +88,68 @@ button@4 { }; &pinctrl { + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "pc_1"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + gpio_joystick_pins: gpio-joystick-pins { gpio_joystick_cfg { pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3"; @@ -145,6 +207,17 @@ uart0_tx_cfg { }; }; +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + &mmcsd { status = "okay"; bus-width = <4>; From 930a43e2e6ea2069e1fbc475b9af9d05315b0591 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Fri, 29 May 2015 23:09:52 +0200 Subject: [PATCH 15/17] ARM: dts: lpc4357-ea4357: add uart3 Enable UART3 that is routed to the J17 DSUB9 connector on the EA4357 devkit. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 22 +++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 0d04a8e8dbc1..3a3ba16fe690 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -205,6 +205,22 @@ uart0_tx_cfg { bias-pull-down; }; }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + input-schmitt-disable; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p9_3"; + function = "uart3"; + bias-pull-down; + }; + }; }; &enet_tx_clk { @@ -231,3 +247,9 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; }; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; From a8069fafe8a3ce1567e2394b8551902ede300445 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Sun, 21 Jun 2015 20:23:48 -0300 Subject: [PATCH 16/17] of: add vendor prefix for CIAA project CIAA stands for Argentine Open Industrial Computer. The CIAA project is an initiative sponsored by universities and private companies. Its main goal is to promote local embedded systems development. Among other devices, the project developed a NXP LPC4337-based reference design. Signed-off-by: Ezequiel Garcia Signed-off-by: Joachim Eastwood --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index d444757c4d9e..c2f0af7b276d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -46,6 +46,7 @@ chipone ChipOne chipspark ChipSPARK chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. +ciaa Computadora Industrial Abierta Argentina cirrus Cirrus Logic, Inc. cloudengines Cloud Engines, Inc. cnm Chips&Media, Inc. From e794db2ccbb587198e74fbe4fc035131875bf1e4 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 1 Jun 2015 22:57:16 -0300 Subject: [PATCH 17/17] ARM: dts: add DT for CIAA LPC4337 industrial computer Add basic support for CIAA (Argentine Open Industrial Computer) LPC4337 board. This commit enables the following peripherals: * UART * SSP * Ethernet Signed-off-by: Ezequiel Garcia Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/lpc4337-ciaa.dts | 187 +++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/arm/boot/dts/lpc4337-ciaa.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..d43f55034eed 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -211,6 +211,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/lpc4337-ciaa.dts new file mode 100644 index 000000000000..5f500c1ad89c --- /dev/null +++ b/arch/arm/boot/dts/lpc4337-ciaa.dts @@ -0,0 +1,187 @@ +/* + * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) + * + * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + */ +/dts-v1/; + +#include "lpc18xx.dtsi" +#include "lpc4357.dtsi" + +#include "dt-bindings/gpio/gpio.h" + +/ { + model = "CIAA NXP LPC4337"; + compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350"; + + aliases { + serial0 = &uart2; + serial1 = &uart3; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart2; + }; + + memory { + device_type = "memory"; + reg = <0x28000000 0x0800000>; /* 8 MB */ + }; +}; + +&pinctrl { + enet_rmii_pins: enet-rmii-pins { + enet_rmii_rxd_cfg { + pins = "p1_15", "p0_0"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_txd_cfg { + pins = "p1_18", "p1_20"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_rx_dv_cfg { + pins = "p1_16"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_rmii_tx_en_cfg { + pins = "p0_1"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_ref_clk_cfg { + pins = "p1_19"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdio_cfg { + pins = "p1_17"; + function = "enet"; + bias-disable; + input-enable; + input-schmitt-disable; + }; + + enet_mdc_cfg { + pins = "p7_7"; + function = "enet"; + slew-rate = <1>; + bias-disable; + input-enable; + input-schmitt-disable; + }; + }; + + ssp_pins: ssp-pins { + ssp1_cs { + pins = "p6_7"; + function = "gpio"; + bias-pull-up; + bias-disable; + }; + + ssp1_miso_mosi { + pins = "p1_3", "p1_4"; + function = "ssp1"; + slew-rate = <1>; + bias-pull-down; + input-enable; + input-schmitt-disable; + }; + + ssp1_sck { + pins = "pf_4"; + function = "ssp1"; + slew-rate = <1>; + bias-disable; + }; + }; + + uart2_pins: uart2-pins { + uart2_rx_cfg { + pins = "p7_2"; + function = "uart2"; + bias-disable; + input-enable; + }; + + uart2_tx_cfg { + pins = "p7_1"; + function = "uart2"; + bias-disable; + }; + }; + + uart3_pins: uart3-pins { + uart3_rx_cfg { + pins = "p2_4"; + function = "uart3"; + bias-disable; + input-enable; + }; + + uart3_tx_cfg { + pins = "p2_3"; + function = "uart3"; + bias-disable; + }; + }; +}; + +&enet_tx_clk { + clock-frequency = <50000000>; +}; + +&mac { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&enet_rmii_pins>; +}; + +&ssp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp_pins>; + cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>; + num-cs = <1>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +};