cxl: Increase timeout for detection of AFU mmio hang

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PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions, which is still (easily) the case here.

Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Tested-by: Frank Haverkamp <haver@linux.vnet.ibm.com>
Tested-by: Manoj Kumar <manoj@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

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Frederic Barrat 2016-04-19 18:34:24 +02:00 • committed by Michael Ellerman

parent e009a7e858

commit 4aec6ec0da

1 changed files with 3 additions and 1 deletions

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drivers/misc/cxl/pci.c

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