drm/i915: Fix and cleanup DPLL calculation for Ironlake

Browse source

When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.

This fixes DPLL clock issue against one monitor at 1680x1050@60hz.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

...

This commit is contained in:

Zhenyu Wang 2009-11-02 07:52:29 +00:00 • committed by Eric Anholt

parent ba86bf8bfc

commit 4bfe6b6876

1 changed files with 6 additions and 9 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

15

drivers/gpu/drm/i915/intel_display.c

View file