drm/amd/display: Not check wm and clk change flag in optimized bandwidth.

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[Why]
System isn't able to enter S0i3 due to not send display count 0 to smu.
When dpms off, clk changed flag is cleared alreay, and it is checked
when doing optimized bandwidth, and update clocks is bypassed due to the
flag is unset.

[How]
Remove check flag incide the function since watermark values and clocks
values are checked during update to determine whether to perform it, no
need to check it again outside the function.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Yongqiang Sun 2020-02-26 14:25:29 -05:00 • committed by Alex Deucher

parent cc4935087e

commit 4c631826e0

3 changed files with 23 additions and 35 deletions

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4

drivers/gpu/drm/amd/display/dc/core/dc.c

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28

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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24

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

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