i2c-designware: Set Tx/Rx FIFO threshold levels

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As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.

In other words, we must never make "Tx FIFO underrun" happen during
a transaction, except for the last byte.  For the safety's sake, we'd
make TX_EMPTY interrupt get triggered every time one byte is processed.

The Rx FIFO threshold needs to be set as well.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>

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Shinya Kuribayashi 2009-11-06 21:48:12 +09:00 • committed by Ben Dooks

parent 0774539948

commit 4cb6d1d6da

1 changed files with 6 additions and 0 deletions

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drivers/i2c/busses/i2c-designware.c

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