drm/i915: Reoder BDW+ EU/slice fuse bits

Browse source

We customarily define the bits of a register in big endian
order. Reorder the BDW+ fuse bits to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-11-ville.syrjala@linux.intel.com

...

This commit is contained in:

Ville Syrjälä 2025-02-12 01:19:38 +02:00 • committed by Andi Shyti

parent d75131164e

commit 4cdaba1bb0

1 changed files with 16 additions and 15 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

31

drivers/gpu/drm/i915/gt/intel_gt_regs.h

View file