LoongArch: KVM: Add delay until timer interrupt injected

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commit d3c9515e4f upstream.

When timer is fired in oneshot mode, CSR.TVAL will stop with value -1
rather than 0. However when the register CSR.TVAL is restored, it will
continue to count down rather than stop there.

Now the method is to write 0 to CSR.TVAL, wait to count down for 1 cycle
at least, which is 10ns with a timer freq 100MHz, and then retore timer
interrupt status. Here add 2 cycles delay to assure that timer interrupt
is injected.

With this patch, timer selftest case passes to run always.

Cc: stable@vger.kernel.org
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Bibo Mao 2025-11-09 16:02:09 +08:00 • committed by Greg Kroah-Hartman

parent 70c130b1cf

commit 4d9b0ea629

1 changed files with 2 additions and 0 deletions

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arch/loongarch/kvm/timer.c

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