MIPS: ath79: rework IP2/IP3 interrupt handling

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The current implementation assumes that flushing the
DDR writeback buffer is required for IP2/IP3 interrupts,
however this is not true for all SoCs.

Use SoC specific IP2/IP3 handlers instead of flushing
the buffers in the dispatcher code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Gabor Juhos 2012-03-14 10:45:24 +01:00 • committed by Ralf Baechle

parent 5b5b544ed3

commit 4dbcbdf813

1 changed files with 72 additions and 20 deletions

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arch/mips/ath79/irq.c

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