spi: spi-cadence: supports transmission with bits_per_word of 16 and 32

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The default FIFO data width of the Cadence SPI IP is 8 bits, but
the hardware supports configurations of 16 bits and 32 bits.
This patch enhances the driver to support communication with both
16-bits and 32-bits FIFO data widths.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://patch.msgid.link/20251031073003.3289573-3-jun.guo@cixtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Jun Guo 2025-10-31 15:30:02 +08:00 • committed by Mark Brown

parent 55b5d192ba

commit 4e00135b2d

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drivers/spi/spi-cadence.c

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