media: ccs-pll: Add support for extended input PLL clock divider

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CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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Sakari Ailus 2020-06-23 13:40:32 +02:00 • committed by Mauro Carvalho Chehab

parent ae502e08f4

commit 4e1e8d240d

3 changed files with 7 additions and 1 deletions

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4

drivers/media/i2c/ccs-pll.c

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1

drivers/media/i2c/ccs-pll.h

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3

drivers/media/i2c/ccs/ccs-core.c

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