clk: samsung: clk-pll: Add support for pll_1418x

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pll1418x is used in Exynos7885 SoC for USB PHY clock.
Operation-wise it is very similar to pll0822x, except that MDIV is only
9 bits wide instead of 10, and we use the CON1 register in the PLL
macro's "con" parameter instead of CON3 like this:

	PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
	    PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
	    pll_usb_rate_table),

Technically the PLL should work fine with pll0822x code if the PLL
tables are correct, but it's more "correct" to actually update the mask.

Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240816175034.769628-2-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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David Virag 2024-08-16 19:50:31 +02:00 • committed by Krzysztof Kozlowski

parent ae07389413

commit 4e39e5b843

2 changed files with 16 additions and 3 deletions

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18

drivers/clk/samsung/clk-pll.c

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1

drivers/clk/samsung/clk-pll.h

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