drm/i915: Pipe timing registers need an offset on VLV

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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-01-24 15:29:46 +02:00 • committed by Daniel Vetter

parent 67d62c5746

commit 4e8e7eb703

1 changed files with 18 additions and 18 deletions

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drivers/gpu/drm/i915/i915_reg.h

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