From 4ec4ccdaace40397638c305c0a36b423d2142a93 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 6 Mar 2026 15:34:15 +0100 Subject: [PATCH] PCI: rzg3s-host: Make configuration reset lines optional Some SoC variants such as RZ/G3E handle configuration reset control through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets optional by using devm_reset_control_bulk_get_optional_exclusive() to allow SoCs to use alternative or complementary reset control mechanisms. Signed-off-by: John Madieu Signed-off-by: Manivannan Sadhasivam Tested-by: Lad Prabhakar # RZ/V2N EVK Tested-by: Claudiu Beznea Reviewed-by: Claudiu Beznea Link: https://patch.msgid.link/20260306143423.19562-9-john.madieu.xa@bp.renesas.com --- drivers/pci/controller/pcie-rzg3s-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index f5a0b7c6e773..c818651c0b75 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1188,9 +1188,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) if (ret) return ret; - return devm_reset_control_bulk_get_exclusive(host->dev, - data->num_cfg_resets, - host->cfg_resets); + return devm_reset_control_bulk_get_optional_exclusive(host->dev, + data->num_cfg_resets, + host->cfg_resets); } static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)