drm/radeon: put UVD PLLs in bypass mode

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Just power down the PLL when we get a VCLK or DCLK of zero.
Enabling the bypass mode early should also allow us to
switch UVD clocks on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Christian König 2013-04-18 15:25:58 +02:00 • committed by Alex Deucher

parent 9054ae1ce3

commit 4ed108352d

3 changed files with 41 additions and 23 deletions

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22

drivers/gpu/drm/radeon/evergreen.c

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20

drivers/gpu/drm/radeon/rv770.c

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22

drivers/gpu/drm/radeon/si.c

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