clk: rockchip: Add 1.6GHz PLL rate for rk3399

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We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Derek Basehore 2018-03-13 13:37:19 -07:00 • committed by Heiko Stuebner

parent 60cf09e45f

commit 4ee3fd4abe

1 changed files with 1 additions and 0 deletions

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drivers/clk/rockchip/clk-rk3399.c

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