KVM: x86/pmu: Limit the maximum number of supported Intel GP counters

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The Intel Architectural IA32_PMCx MSRs addresses range allows for a
maximum of 8 GP counters, and KVM cannot address any more.  Introduce a
local macro (named KVM_INTEL_PMC_MAX_GENERIC) and use it consistently to
refer to the number of counters supported by KVM, thus avoiding possible
out-of-bound accesses.

Suggested-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Message-Id: <20220919091008.60695-2-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Like Xu 2022-09-19 17:10:07 +08:00 • committed by Paolo Bonzini

parent 8631ef59b6

commit 4f1fa2a1bb

4 changed files with 15 additions and 9 deletions

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6

arch/x86/include/asm/kvm_host.h

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2

arch/x86/kvm/pmu.c

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4

arch/x86/kvm/vmx/pmu_intel.c

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12

arch/x86/kvm/x86.c

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