drm/xe/xe3p_lpg: Restrict UAPI to enable L2 flush optimization

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When set, starting xe3p_lpg, the L2 flush optimization
feature will control whether L2 is in Persistent or
Transient mode through monitoring of media activity.

To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
media type is detected.

Tighten UAPI validation to restrict userptr, svm and
dmabuf mappings to be either 2WAY or XA+1WAY

V5(Thomas): logic correction
V4(MattA): Modify uapi doc and commit
V3(MattA): check valid op and pat_index value
V2(MattA): validate dma-buf bos and madvise pat-index

Acked-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Acked-by: Carl Zhang <carl.zhang@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260305121902.1892593-9-tejas.upadhyay@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

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This commit is contained in:

Tejas Upadhyay 2026-03-05 17:49:06 +05:30

parent 411389d29e

commit 4f39a194d4

5 changed files with 38 additions and 1 deletions

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3

drivers/gpu/drm/xe/xe_guc.c

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1

drivers/gpu/drm/xe/xe_guc_fwif.h

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8

drivers/gpu/drm/xe/xe_vm.c

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23

drivers/gpu/drm/xe/xe_vm_madvise.c

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4

include/uapi/drm/xe_drm.h

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