drm/i915: Set i9xx sdvo clock limits according to specifications

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The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Patrik Jakobsson 2013-02-13 22:20:22 +01:00 • committed by Daniel Vetter

parent 53a7d2d15e

commit 4f7dfb6788

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/i915/intel_display.c

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