drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming

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Make sure all the DP/HDMI/HDMI-FRL flags are programmed in all the modes
the PLL is configured.

Atm the DP mode flag is not programmed in case the PLL is configured for
HDMI mode for instance. This is incorrect after HW reset, since the DP
mode flag is asserted after reset, hence would need to be cleared for
HDMI, but also incorrect because of the same reason after configuring
the PLL to HDMI mode after it was used in DP mode (for instance on a
DP++ connector).

There is a similar issue with the HDMI-FRL flag, potentially remaining
set when configuring the PLL in DP mode.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-6-mika.kahola@intel.com

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Imre Deak 2025-10-15 15:54:44 +03:00 • committed by Mika Kahola

parent b02c9b5e6f

commit 4fd6053274

1 changed files with 14 additions and 11 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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