drm/i915/xehp: Add Compute CS IRQ handlers

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Add execlists and GuC interrupts for compute CS into existing IRQ handlers.

All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.

CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.

BSpec: 50844, 54029, 54030, 53223, 53224.
Original-author: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-4-matthew.d.roper@intel.com

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This commit is contained in:

Matt Roper 2022-03-01 15:15:39 -08:00

parent 4b88ad503d

commit 505c4857fb

3 changed files with 19 additions and 1 deletions

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15

drivers/gpu/drm/i915/gt/intel_gt_irq.c

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3

drivers/gpu/drm/i915/gt/intel_gt_regs.h

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2

drivers/gpu/drm/i915/i915_drv.h

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