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drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming
Since the clock rate is derived from the PLL divider values it can have a +-1kHz difference wrt. the reference rates in the comparison Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260119093757.2850233-11-mika.kahola@intel.com
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