drm/i915/dip: Store and use AS SDP transmission line from crtc state

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The driver currently computes the Adaptive Sync SDP transmission line
directly at programming time. Instead, compute and store the
AS SDP transmission line in the crtc state and use it when programming the
EMP_AS_SDP_TL register.

We get the clear picture about the SDPs and guardband only in
intel_dp_sdp_compute_config_late() therefore we must configure the
AS SDP transmission line at this point when AS SDP is enabled in
crtc_state.

This prepares the ground for supporting programmable transmission lines
for additional DP SDPs.

While moving the helper into intel_dip.c, drop the
intel_crtc_has_dp_encoder() check instead of relocating it. It was
needed in the old VRR write path shared by other encoderes as well, but
intel_dip_sdp_tl_compute_config_late() is only reached via DP, so HDMI
never sets crtc_state->dip.emp_as_sdp_tl and it stays 0 by default.

v2:
- Move the helper into intel_dip.c and drop the
  intel_crtc_has_dp_encoder() check.
- Drop the redundant checks. (Suraj)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260915164657.3429075-7-ankit.k.nautiyal@intel.com

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This commit is contained in:

Ankit Nautiyal 2026-09-15 22:16:47 +05:30

parent 5aa79d2e99

commit 50dae5bab5

4 changed files with 19 additions and 9 deletions

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2

drivers/gpu/drm/i915/display/intel_ddi.c

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20

drivers/gpu/drm/i915/display/intel_dip.c

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3

drivers/gpu/drm/i915/display/intel_dip.h

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3

drivers/gpu/drm/i915/display/intel_dp.c

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