clk: st: STiH407: Support for clockgenC0

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The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Gabriel FERNANDEZ 2014-07-15 17:20:27 +02:00 • committed by Mike Turquette

parent fc755c8bc8

commit 51306d56ba

2 changed files with 83 additions and 0 deletions

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51

drivers/clk/st/clkgen-fsyn.c

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32

drivers/clk/st/clkgen-pll.c

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