drm/tegra: sor: Write correct head state registers

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The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2015-07-30 18:47:07 +02:00

parent 8044449556

commit 51511d05de

1 changed files with 6 additions and 4 deletions

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drivers/gpu/drm/tegra/sor.c

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