drm/i915/glk: Set DCC delay range 2 in PLL enable sequence

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Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.

v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com

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Ander Conselvan de Oliveira 2016-12-02 10:23:52 +02:00

parent 0a116ce895

commit 51b3ee35af

2 changed files with 21 additions and 0 deletions

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15

drivers/gpu/drm/i915/i915_reg.h

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6

drivers/gpu/drm/i915/intel_dpll_mgr.c

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