From 52a484f3ef5b36c063d8fca7b8763c1a9676c625 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 3 Sep 2026 11:22:10 +0530 Subject: [PATCH] drm/amdgpu: Move GC v12.1 spm vmid init to hw init GC reset is not released during sw init and hence it shouldn't be accessed. Move spm vmid programming to hw init phase. This programming may later be overridden with the job's vmid. Fixes: ad5f1ee0a9b0 ("drm/amdgpu: Add initial support for gfx v12_1") Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 1a09bd41f795..db541939555b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -213,6 +213,8 @@ static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); static void gfx_v12_1_xcc_update_medium_grain_clock_gating( struct amdgpu_device *adev, bool enable, int xcc_id, bool force); +static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid); static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, int mem_space, int opt, uint32_t addr0, @@ -544,7 +546,7 @@ static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) { const struct cs_section_def *cs_data; - int r, i, num_xcc; + int r; adev->gfx.rlc.cs_data = gfx12_cs_data; @@ -557,13 +559,6 @@ static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) return r; } - /* init spm vmid with 0xf */ - num_xcc = NUM_XCC(adev->gfx.xcc_mask); - for (i = 0; i < num_xcc; i++) { - if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); - } - return 0; } @@ -1836,6 +1831,9 @@ static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, { int r; + /* init spm vmid with 0xf */ + gfx_v12_1_update_spm_vmid(adev, xcc_id, NULL, 0xf); + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { gfx_v12_1_xcc_init_csb(adev, xcc_id);