drm/i915/psr: Fix PSR sink enable sequence

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According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240911151836.16800-1-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

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Ville Syrjälä 2024-09-11 18:18:36 +03:00

parent 2478e2234d

commit 52c4abeec6

1 changed files with 3 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_psr.c

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