ath9k: Fix ack SIFS time for quarter/half channels

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Ack timing generation has to be adapted for 5/10 MHz channels.
Do it by properly initializing ack shift field in TXSIFS
register. Ack shift assumes channel width of 2.5 Mhz so
value zero means 2.5 MHz, 1 is 5 MHz and so on.

Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

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Wojciech Dubowik 2018-02-20 15:42:00 +01:00 • committed by Kalle Valo

parent 91f1ee65d9

commit 52c528ffaf

1 changed files with 7 additions and 1 deletions

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drivers/net/wireless/ath/ath9k/hw.c

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