arm64: dts: qcom: glymur: fix PCIe SMMU interrupts

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The PCIe SMMUv3 wired interrupts are routed to GIC extended SPI INTIDs
4100, 4098 and 4096. Describe them as ESPIs with the ESPI-relative
interrupt numbers instead of regular SPIs 964, 962 and 960.

Assisted-by: Codex:GPT-5.5
Fixes: 41b6e8db40 ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260611-glymur-pcie-smmu-espi-v1-1-5effbaa3e1af@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Bjorn Andersson 2026-06-11 19:00:44 +00:00 • committed by Bjorn Andersson

parent dc59e4fea9

commit 52c7084c8f

1 changed files with 3 additions and 3 deletions

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arch/arm64/boot/dts/qcom/glymur.dtsi

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