clk: meson: axg: mark fdiv2 and fdiv3 as critical

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Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor
uses the fdiv2 and fdiv3 to, among other things, provide the cpu
clock.

Until clock hand-off mechanism makes its way to CCF and the generic
SCPI claims platform specific clocks, these clocks must be marked as
critical to make sure they are never disabled when needed by the
co-processor.

Fixes: 05f814402d ("clk: meson: add fdiv clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Jerome Brunet 2018-11-08 10:31:23 +01:00 • committed by Greg Kroah-Hartman

parent a98af72325

commit 52cad794b4

1 changed files with 13 additions and 0 deletions

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drivers/clk/meson/axg.c

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