drm/amd/display: adopt DP2.0 LT SCR revision 8

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revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment
in one 5 byte write aux transaction.
It specifies to read aux rd interval value as soon as we turn on TPS1
pattern.

Cc: Wayne Lin <wayne.lin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Wenjing Liu 2021-06-14 18:31:21 -04:00 • committed by Alex Deucher

parent ed0ffb5dcd

commit 5354b2bd28

1 changed files with 13 additions and 8 deletions

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

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