From b0ab681285aa66064f2de5b74191c0cabba381ff Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 7 Nov 2017 19:45:01 -0800 Subject: [PATCH 1/8] arm64: dts: msm8916: Add missing #phy-cells Add a missing #phy-cells to the dsi-phy, to silence dtc warning. Cc: Archit Taneja Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support") Signed-off-by: Bjorn Andersson Reviewed-by: Archit Taneja Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6b2127a6ced1..09ac5c43807e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -906,6 +906,7 @@ dsi_phy0: dsi-phy@1a98300 { "dsi_phy_regulator"; #clock-cells = <1>; + #phy-cells = <0>; clocks = <&gcc GCC_MDSS_AHB_CLK>; clock-names = "iface_clk"; From 566bd8902e7fa20bd412ed753e09e89c1c96939c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 30 Nov 2017 21:27:32 -0800 Subject: [PATCH 2/8] arm64: dts: msm8916: Correct ipc references for smsm SMSM is not symmetrical, the incoming bits from WCNSS are available at index 6, but the outgoing host id for WCNSS is 3. Further more, upstream references the base of APCS (in contrast to downstream), so the register offset of 8 must be included. Fixes: 1fb47e0a9ba4 ("arm64: dts: qcom: msm8916: Add smsm and smp2p nodes") Cc: stable@vger.kernel.org Reported-by: Ramon Fried Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 09ac5c43807e..b84c0ca4f84a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1436,8 +1436,8 @@ smsm { #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 0 13>; - qcom,ipc-6 = <&apcs 0 19>; + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; apps_smsm: apps@0 { reg = <0>; From 237f7bec2508e2bdfd658075b88e67575c160370 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:33 -0500 Subject: [PATCH 3/8] arm64: dts: qcom: pm8916: fix wcd_codec indentation Indentation did not respect kernel standards, so fix that for the usual indent with tabs, align with spaces. While at it, remove some empty lines before and after the closing parenthesis of this block. Signed-off-by: Damien Riegel Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 82 ++++++++++++++-------------- 1 file changed, 40 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 0223e60d8b6a..196b1c0ceb9b 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -97,47 +97,45 @@ pm8916_1: pm8916@1 { #address-cells = <1>; #size-cells = <0>; - wcd_codec: codec@f000 { - compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000 0x200>; - reg-names = "pmic-codec-core"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, - <0x1 0xf0 0x1 IRQ_TYPE_NONE>, - <0x1 0xf0 0x2 IRQ_TYPE_NONE>, - <0x1 0xf0 0x3 IRQ_TYPE_NONE>, - <0x1 0xf0 0x4 IRQ_TYPE_NONE>, - <0x1 0xf0 0x5 IRQ_TYPE_NONE>, - <0x1 0xf0 0x6 IRQ_TYPE_NONE>, - <0x1 0xf0 0x7 IRQ_TYPE_NONE>, - <0x1 0xf1 0x0 IRQ_TYPE_NONE>, - <0x1 0xf1 0x1 IRQ_TYPE_NONE>, - <0x1 0xf1 0x2 IRQ_TYPE_NONE>, - <0x1 0xf1 0x3 IRQ_TYPE_NONE>, - <0x1 0xf1 0x4 IRQ_TYPE_NONE>, - <0x1 0xf1 0x5 IRQ_TYPE_NONE>; - interrupt-names = "cdc_spk_cnp_int", - "cdc_spk_clip_int", - "cdc_spk_ocp_int", - "mbhc_ins_rem_det1", - "mbhc_but_rel_det", - "mbhc_but_press_det", - "mbhc_ins_rem_det", - "mbhc_switch_int", - "cdc_ear_ocp_int", - "cdc_hphr_ocp_int", - "cdc_hphl_ocp_det", - "cdc_ear_cnp_int", - "cdc_hphr_cnp_int", - "cdc_hphl_cnp_int"; - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; - #sound-dai-cells = <1>; - - }; - + wcd_codec: codec@f000 { + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000 0x200>; + reg-names = "pmic-codec-core"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; + #sound-dai-cells = <1>; + }; }; }; From 06c73e621319c7558ea99759f2cd4cef22e153bc Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:34 -0500 Subject: [PATCH 4/8] arm64: dts: qcom: msm8916-pins: remove assignments to bias-disable Drop assignments to bias-disable as the documentation [1] states that this property doesn't take a value. Other occurrences of this property respect that. [1] Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt Signed-off-by: Damien Riegel Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 4cb0b5834143..c67ad8ed8b60 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -278,7 +278,7 @@ pinmux { pinconf { pins = "gpio6", "gpio7"; drive-strength = <16>; - bias-disable = <0>; + bias-disable; }; }; @@ -290,7 +290,7 @@ pinmux { pinconf { pins = "gpio6", "gpio7"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -302,7 +302,7 @@ pinmux { pinconf { pins = "gpio14", "gpio15"; drive-strength = <16>; - bias-disable = <0>; + bias-disable; }; }; @@ -314,7 +314,7 @@ pinmux { pinconf { pins = "gpio14", "gpio15"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -326,7 +326,7 @@ pinmux { pinconf { pins = "gpio22", "gpio23"; drive-strength = <16>; - bias-disable = <0>; + bias-disable; }; }; @@ -338,7 +338,7 @@ pinmux { pinconf { pins = "gpio22", "gpio23"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; From 24fe618b2d9a10091454def66838b786f0649855 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:36 -0500 Subject: [PATCH 5/8] arm64: dts: qcom: msm8916: drop unused board-specific nodes These nodes reserve and configure some pins as GPIOs. They are not generic pinctrls, they actually belong to board files but they are not used by any other node, so just drop them altogether. Signed-off-by: Damien Riegel Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 52 ---------------------- 1 file changed, 52 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index c67ad8ed8b60..98f7404f5f8d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -505,32 +505,6 @@ pinconf { }; }; - ext-codec-lines { - ext_codec_lines_act: lines_on { - pinmux { - function = "gpio"; - pins = "gpio67"; - }; - pinconf { - pins = "gpio67"; - drive-strength = <8>; - bias-disable; - output-high; - }; - }; - ext_codec_lines_sus: lines_off { - pinmux { - function = "gpio"; - pins = "gpio67"; - }; - pinconf { - pins = "gpio67"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - cdc-pdm-lines { cdc_pdm_lines_act: pdm_lines_on { pinmux { @@ -695,32 +669,6 @@ pinconf { }; }; - cross-conn-det { - cross_conn_det_act: lines_on { - pinmux { - function = "gpio"; - pins = "gpio120"; - }; - pinconf { - pins = "gpio120"; - drive-strength = <8>; - output-low; - bias-pull-down; - }; - }; - cross_conn_det_sus: lines_off { - pinmux { - function = "gpio"; - pins = "gpio120"; - }; - pinconf { - pins = "gpio120"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - wcnss_pin_a: wcnss-active { pinmux { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; From 500566e0e9fc1e5f3d260c691c58071cab596598 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:41 -0500 Subject: [PATCH 6/8] arm64: dts: qcom: msm8916: normalize I2C and SPI nodes The QUP core can be used either for I2C or SPI, so the same IP is mapped by a driver or the other. SPI bindings use a leading 0 for the start address and a size of 0x600, I2C bindings don't have the leading 0 and have a size 0x1000. To make them more similar, add the leading 0 to I2C bindings and changes the size to 0x500 for all of them, as this is the actual size of these blocks. Also align the second entry of the clocks array. Signed-off-by: Damien Riegel Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index b84c0ca4f84a..e51b04900726 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -355,7 +355,7 @@ blsp_dma: dma@7884000 { blsp_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x600>; + reg = <0x078b5000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -372,7 +372,7 @@ blsp_spi1: spi@78b5000 { blsp_spi2: spi@78b6000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x600>; + reg = <0x078b6000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -389,7 +389,7 @@ blsp_spi2: spi@78b6000 { blsp_spi3: spi@78b7000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x600>; + reg = <0x078b7000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -406,7 +406,7 @@ blsp_spi3: spi@78b7000 { blsp_spi4: spi@78b8000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x600>; + reg = <0x078b8000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -423,7 +423,7 @@ blsp_spi4: spi@78b8000 { blsp_spi5: spi@78b9000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x600>; + reg = <0x078b9000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -440,7 +440,7 @@ blsp_spi5: spi@78b9000 { blsp_spi6: spi@78ba000 { compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078ba000 0x600>; + reg = <0x078ba000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -457,10 +457,10 @@ blsp_spi6: spi@78ba000 { blsp_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b6000 0x1000>; + reg = <0x078b6000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; @@ -472,10 +472,10 @@ blsp_i2c2: i2c@78b6000 { blsp_i2c4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x1000>; + reg = <0x078b8000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; @@ -487,10 +487,10 @@ blsp_i2c4: i2c@78b8000 { blsp_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78ba000 0x1000>; + reg = <0x078ba000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; From 3785630d04ee7313ef54e4d051f0ca9e59e70065 Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:40 -0500 Subject: [PATCH 7/8] arm64: dts: qcom: msm8916-pins: move sdhc2 cd node with its siblings Nodes relative to the first sdhc node were interlaced with node of the second sdhc. Move sdhc2_cd_pin with its siblings to prevent that. Also rename the grouping node from sdhc2_cd_pin to pmx_sdc2_cd_pin, as "pmx_sdc" is the prefix used by other nodes. Signed-off-by: Damien Riegel Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 50 +++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 98f7404f5f8d..68fb589a7297 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -342,31 +342,6 @@ pinconf { }; }; - sdhc2_cd_pin { - sdc2_cd_on: cd_on { - pinmux { - function = "gpio"; - pins = "gpio38"; - }; - pinconf { - pins = "gpio38"; - drive-strength = <2>; - bias-pull-up; - }; - }; - sdc2_cd_off: cd_off { - pinmux { - function = "gpio"; - pins = "gpio38"; - }; - pinconf { - pins = "gpio38"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - pmx_sdc1_clk { sdc1_clk_on: clk_on { pinmux { @@ -505,6 +480,31 @@ pinconf { }; }; + pmx_sdc2_cd_pin { + sdc2_cd_on: cd_on { + pinmux { + function = "gpio"; + pins = "gpio38"; + }; + pinconf { + pins = "gpio38"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sdc2_cd_off: cd_off { + pinmux { + function = "gpio"; + pins = "gpio38"; + }; + pinconf { + pins = "gpio38"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + cdc-pdm-lines { cdc_pdm_lines_act: pdm_lines_on { pinmux { From 342a2922acb0f1be6b5e937427545f04c9d0a7ee Mon Sep 17 00:00:00 2001 From: Damien Riegel Date: Thu, 7 Dec 2017 10:19:35 -0500 Subject: [PATCH 8/8] arm64: dts: qcom: msm8916-pins: keep cdc_dmic pins in suspend mode This node was the only one that didn't have the same set of pins in active and suspend mode. Signed-off-by: Damien Riegel Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 68fb589a7297..390a2fa28514 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -661,6 +661,14 @@ pinconf { }; }; cdc_dmic_lines_sus: dmic_lines_off { + pinmux_dmic0_clk { + function = "dmic0_clk"; + pins = "gpio0"; + }; + pinmux_dmic0_data { + function = "dmic0_data"; + pins = "gpio1"; + }; pinconf { pins = "gpio0", "gpio1"; drive-strength = <2>;