perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X

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Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.

To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1374138144-17278-1-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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Yan, Zheng 2013-07-18 17:02:23 +08:00 • committed by Ingo Molnar

parent ea79ca0de0

commit 53ad044720

1 changed files with 13 additions and 9 deletions

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arch/x86/kernel/cpu/perf_event_intel.c

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