clk: renesas: r9a07g044: Fix OSTM1 module clock name

Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.

Fixes: 161450134a ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-05-02 14:35:02 +02:00
commit 53c58c08b4